The present invention described herein relates to technology for power-up control in semiconductor memory apparatuses. In particular, the present invention described herein relates to a technique capable of reducing current consumption during a power-up operation, suitable for a low-power DRAM.
Most semiconductor memory apparatuses, especially, DRAMs, usually use basic settings or initializing operations necessary for chip operations before or after stabilizing power supplies from external power sources. Specifically, it is necessary to control the voltage level of a latch circuit or specific node connected to an input buffer in a DRAM. Further, a chip designer is also required to set the voltage level of the latch circuit or specific node at a level with options. This operation is generally accomplished by a power-up circuit, which is generally employed in a DRAM.
The power-up circuit is also used to determine the time to generate an internal voltage in a DRAM chip. In other words, the power-up circuit generates a specific signal when an external power source voltage rises up to a target voltage level, outputting an internal voltage with reference to the point of the specific signal. For instance, if the external power source voltage is 2.5V, the specific signal is generated when the external power source voltage arrives around 1.2V.
With respect to these facts, FIG. 1 shows a conventional power-up circuit.
As illustrated in FIG. 1, the conventional power-up circuit includes a power-up signal generating section 10, a pulse generating section 20, and an initializing section 30.
The power-up signal generator 10 receives an external power source voltage VDD and a ground voltage VSS and provides the initializing section 30 with a power-up signal PWRUP that is set when the external power source voltage VDD reaches a specific voltage (i.e., a target voltage). The power-up signal generating section 10 also outputs an inverted power-up signal PWRUPB to the pulse generating section 20.
The pulse generating section 20 provides the initializing section 30 with a short pulse PWRUP_P with reference to a point at which the inverted power-up signal PWRUPB is supplied from the power-up signal generating section 10. The initializing section 30 initializes the internal circuits of the semiconductor memory apparatus in accordance with the power-up signal PWRUP of the power-up signal generating section 10 and the pulse PWRUP_P of the pulse generating section 20.
Especially, the initializing section 30 initializes the part where PMOS and NMOS transistors forming a CMOS circuit are turned on at the same time during the short period of the pulse PWRUP_P. Namely, the pulse generating section 20 provides the pulse PWRUP_P in order to mostly reduce the consumption of a direct current through the PMOS and NMOS transistors that are turned on at the same time.
FIG. 2 is a detailed circuit diagram of the power-up signal generating section 10 shown in FIG. 1.
The power-up signal generating section 10 includes a plurality of PMOS transistors P1˜P5, a plurality of NMOS transistors N1˜N6, resistors R1˜R4, and a plurality of inverters IV1˜IV4.
A voltage divider 11 includes the resistors R1˜R4 serially connected to each other, the PMOS transistor P1 coupled to the ground voltage VSS through its gate, and the NMOS transistor N1 coupled to the external power source voltage VDD through its gate. The voltage divider 11 divides the external power source voltage VDD by the resistors R1˜R4 and provides a node A with a specific level among divided voltages. An output from the node A is applied to the gate terminal of the NMOS transistor N2 and the serially connected NMOS transistors N3˜N6, thereby outputting a detection signal DET through the drain terminal of the NMOS transistor N3.
As the voltage divider 11 is designed with a very large resistance so as to restrain current consumption, charges output to the node A may be sensitive to a coupling effect. Therefore, the NMOS transistor N2 contributes to prevent a coupling effect at the node A.
A latch composed of the inverters IV1 and IV2 latches and outputs the detection signal DET. The inverter IV3 logically inverts the output of the latch and outputs the inverted power-up signal PWRUPB, while the inverter IV4 logically inverts the inverted power-up signal PWRUPB and outputs the power-up signal PWRUP.
FIG. 3 is a detailed circuit diagram of the pulse generating section 20 shown in FIG. 1.
The pulse generating section 20 is composed of a delayer 21, inverters IV5 and IV6, and a NAND gate ND1, which is a general, well known circuit pattern. The delayer 21 outputs the inverted power-up signal PWRUPB with a predetermined delay time. The inverter IV5 logically inverts the output of the delayer 21 and outputs the inverted output to the node B. The NAND gate ND1 conducts a NAND operation on the output of the node B and the inverted power-up signal PWRUPB. The inverter IV6 logically inverts the output of the NAND gate ND1 and outputs the pulse PWRUP_P.
FIG. 4 is a timing diagram showing an operation of the power-up circuit shown in FIGS. 1 through 3.
As shown in FIGS. 1 through 3, the conventional power-up circuit is configured to make the voltage level of the node A increase or decrease, as the target voltage set by the voltage divider 11 rises or falls along with the external power source voltage VDD. Also, the conventional power-up circuit detects and outputs a falling time of the voltage level at the node A, the detection signal DET with high level, to generate the power-up signal PWRUP. This can be seen from waveforms of the nodes A and B as shown in FIG. 4.
FIG. 5 is a circuit diagram showing another example of the power-up signal generating section 10 shown in FIG. 1.
The power-up signal generating section 10 of FIG. 5 is constructed without the PMOS and NMOS transistors P1 and N1 in the voltage divider 11 of FIG. 2.
As shown in the timing diagram of FIG. 6, the voltage level of the node A, which is an output of the voltage divider, rises directly along with the external power source voltage VDD. And, according to an output of the node A at a target voltage, the voltage level of the detection signal DET is determined by controlling turn-on states of the serially connected NMOS transistors N3˜N6. The detection signal DET determines the power-up signal PWRUP.
As shown in the timing diagrams shown in FIGS. 4 and 6, such conventional power-up circuits always dissipate, currents I(VDD1) and I(VDD2) due to an operational characteristic of the voltage divider 11 before and after stabilization of the external power source voltage VDD.
The current dissipation through the voltage divider is a great burden to a memory apparatus, e.g., a memory for mobile use, which needs to be operable at low power. Moreover, it normally causes unnecessary current consumption in a memory apparatus.